1. Field of the Invention
The present invention relates to an apparatus for and a method of manufacturing a configurable semiconductor integrated circuit device to which a logic is set by providing the configurable semiconductor integrated circuit device with logic function specifying data. The present invention also relates to an electronic circuit device employing such an apparatus.
2. Description of the Background Art
Fine processing technique for fabrication of a semiconductor device has been developing at a breath-taking speed in recent years, and now, it is possible to form on a single chip a logic circuit which is equivalent to hundreds thousand gates. Improvement in electronic devices which use these increasingly fine circuits has also been rapid. Product cycle becomes shorter and shorter, with which development of a new product in a reduced time receives greatly increased emphasis. Under these circumstances, of various semiconductor device products, those which are suitable for less volume production of many variations, such as a gate array, are becoming essential elements for electronic devices. On the other hand, recent technology development has yielded a configurable semiconductor integrated circuit device called "Field Programmable Gate Array" (abbreviated to "FPGA"). This configurable semiconductor integrated circuit device realizes different logic functions when provided with logic function specifying data which are loaded by a user in a single chip, and therefore, contributes as a key part to quick development of a new electronic device.
A configurable semiconductor integrated circuit device is disclosed in detail, for example, in Japanese Laid-Open Gazette No. 62-115844 (U.S. Pat. No. 4,868,419) and Japanese Laid-Open Gazette No. 63-1114 (U.S. Pat. No. 845, 287).
FIG. 8 is a block diagram showing general concept of a conventional configurable semiconductor integrated circuit device. As shown in FIG. 8, logic elements 2 and memory elements 3 are formed in a configurable semiconductor integrated circuit device 1. The logic elements 2 and the memory elements 3 are connected to each other by connection wires 8. Through regular logic input/output terminals 6, regular logic data are transferred into and out of the logic elements 2. The memory elements 3 receive logic function specifying data through logic function specifying data input terminals 4 and receive an operation mode control signal through operation mode control terminals 5.
In using the configurable semiconductor integrated circuit device, first, an operation mode control signal which calls for a logic function setting mode is given to the memory elements 3 through the operation mode control terminals 5 so that the memory elements 3 enter the logic function setting mode. Next, logic function specifying data which call for desired logic function are given to the memory elements 3 through the logic function specifying data input terminals 4, thereby storing the logic function specifying data in the memory elements 3.
Following this, the operation mode control signal for invoking a regular operation mode is fed to the memory elements 3 through the operation mode control terminals 5 and the memory elements 3 enter the regular operation mode. As a result, the configurable semiconductor integrated circuit device 1 is made ready to execute, through the regular logic input/output terminals 6, logic operations which correspond to the logic function specifying data stored in the memory elements 3.
Thus, even with the same construction, when provided with different logic function specifying data stored in the memory elements 3, the configurable semiconductor integrated circuit device realizes utterly different logic operations. Hence, when a semiconductor device manufacturer needs to produce semiconductor integrated circuits for unspecified applications for a number of different customers, such configurable semiconductor integrated circuit devices are an answer.
This also means that the configurable semiconductor integrated circuit devices can be mass produced as unspecified products, which makes it possible for the manufacturer to lower the price of the products. On the other hand, the user can enjoy an advantage of the configurable semiconductor integrated circuit device that the device alone works as semiconductor integrated circuits having utterly different logics only if the logic function specifying data stored in the memory elements 3 are changed. Moreover, unlike a gate array, complex fabrication process for realizing desired logic functions is not necessary; what is necessary is to set the logic function specifying data in the memory elements 3. Hence, the user of the configurable semiconductor integrated circuit device can develop a semiconductor integrated circuit device which attains wanted logic functions in a reduced time and at less cost.
The configurable semiconductor integrated circuit devices as above are classified into those in which the memory elements 3 are formed by fuse ROMs so that the logic function specifying data can be written into the memory elements 3 only once and those in which the memory elements 3 are formed by rewritable EEPROMs and RAMs so that the logic function specifying data can be written into the memory elements 3 for a plurality of times. The configurable semiconductor integrated circuit devices hereinafter referred to are the latter type in which the logic function specifying data can be written into the memory elements 3 for a plurality of times.
To obtain a semiconductor integrated circuit device having a desired logic function through use of the configurable semiconductor integrated circuit device, generation of logic function specifying data with which the desired logic function is important.
FIG. 9 is an explanatory diagram showing the flow how the logic function specifying data are generated.
Referring to FIG. 9, first, in a logic designing step 11, a logic circuit which realizes a desired logic function is designed as is customarily done in designing an ordinary logic circuit, whereby circuitry diagram data 21 are generated which define the desired logic circuit. In a subsequent arranging and wiring step 12, logic function specifying data 22 are developed from the circuitry diagram data 21.
FIG. 10 is a block diagram showing the details of the arranging and wiring step 12. With reference to FIG. 10, first, the circuitry diagram data 21 are entered and so are data 31 (hereinafter referred to as "FPGA basic data 31") which define basic elements of the configurable semiconductor integrated circuit device. The circuitry diagram data 21 are made based on general logic elements. Meanwhile, only limited logic elements can form, as they are, logic elements of the configurable semiconductor integrated circuit device. Basic logic elements realized in the configurable semiconductor integrated circuit device are registered as the FPGA basic data 31.
In a logic element change step 121, the circuitry diagram data 21 are converted while referring to the FPGA basic data 31 into circuitry data 32 ("FPGA circuitry diagram data 32" hereinafter) for the configurable semiconductor integrated circuit device which consists only of the basic logic elements which are defined in the FPGA basic data 31.
Next, in an arranging step 122, while referring to FPGA construction defining data 33 which define the chip structure of the configurable semiconductor integrated circuit device (the number, the arrangement and structure, the area for wiring of the inner logic element groups 2), the basic logic elements defined on the FPGA circuitry data 32 are assigned to the logic elements 2 of the configurable semiconductor integrated circuit device 1, thereby developing arrangement data 34.
Following this, in a wiring step 123, the connections between the basic logic elements which are assigned by the arranging data 34 are realized in accordance with the FPGA circuitry data 32 and with reference to the FPGA construction defining data 33 and the arranging data 34. As a result, the logic function specifying data 22 are generated which will be then outputted.
The arranging step 122 and the wiring step 123 are attained using a known algorithm which is in popular use during arranging and wiring steps of fabrication of a gate array LSI. For instance, an algorithm such as the minicut method and pair linking method is used in the arranging step 122 while an algorithm such as the channel routing method and the labyrinth method is used in the wiring step 123.
FIG. 11 is an explanatory diagram showing the structure of a conventional FPGA manufacturing apparatus for generating the logic function specifying data 22 which are to be given to the configurable semiconductor integrated circuit device 1.
The FPGA manufacturing apparatus is comprised of an interface circuit 51, a data processing device 52, a display 53, a key board 54 and a magnetic disk 55. The data processing device 52 is connected to the logic function specifying data input terminals 4 and the operation mode control terminals 5 of the configurable semiconductor integrated circuit device 1 through the interface circuit 51. Through the logic function specifying data input terminals 4, the operation mode control terminals 5 and the interface circuit 51, the configurable semiconductor integrated circuit device 1 is set into the operation mode and receives the logic function specifying data 22.
The circuitry diagram data 21, which are developed in the logic designing step 11, are stored in the magnetic disk 55. The data processing device 52 runs a predetermined program based on the circuitry diagram data 21 which are stored in the magnetic disk 55 to perform software processing during which the arranging and wiring step 12 is executed to generate the logic function specifying data 22. During this, the logic function specifying data 22 and the like developed on the magnetic disk 55 can be temporarily stored in the data processing device 52.
As input means for observing a processing performed by the data processing device 52, the key board is used. The display 53 acts as output means.
In setting a logic of the configurable semiconductor integrated circuit device 1 using the logic function specifying data 22, the data processing device 52 operates in the following manner.
First, the data processing device 52 routes the operation mode signal which calls for the logic function setting mode to the configurable semiconductor integrated circuit device 1 through the interface circuit 51 and the operation mode control terminals 5.
The data processing device 52 then runs a program for generating the logic function specifying data 22, thereby developing the logic function specifying data 22. The logic function specifying data 22 are then stored in the memory elements 3 of the configurable semiconductor integrated circuit device 1 through the interface circuit 51 and the logic function specifying data input terminals 4. As a result, the configurable semiconductor integrated circuit device 1 is operative to execute a logic function which is defined by the logic function specifying data 22.
Once the operation mode signal which demands the regular operation mode is given to the configurable semiconductor integrated circuit device 1 through the interface circuit 51 and the operation mode control terminals 5, the configurable semiconductor integrated circuit device 1 is operative to receive and output a signal through the regular logic input/output terminals 6 in accordance with the logic function which is defined by the logic function specifying data 22.
FIG. 12 is an explanatory diagram showing the structure of a programmable emulator apparatus which employs the manufacturing apparatus of FIG. 11. In FIG. 12, the programmable emulator apparatus 100 includes a plurality of configurable semiconductor integrated circuit devices 1. Of the regular logic input/output terminals 6 of each configurable semiconductor integrated circuit device 1, some are connected to a connector 7 and some are connected to some of the regular logic input/output terminals 6 of the other configurable semiconductor integrated circuit device 1.
A logic signal analysis device 40 detects, for every given time period, the logic of a signal which is received at an analysis target signal input terminal 41, and outputs what it has detected to the data processing device 52 from its analysis data output terminal 42. The logic signal analysis device 40 operates under the control of a signal which is received at its analysis control signal input/output terminal 43 from the data processing device 52. The analysis target signal input terminal 41 of the logic signal analysis device 40 is connected to some of the regular logic input/output terminals 6 of the configurable semiconductor integrated circuit devices 1.
The logic function specifying data input terminals 4 and the operation mode control terminals 5 of the configurable semiconductor integrated circuit devices 1 are connected to the data processing device 52 through the interface circuit 51. The rest of the structure is similar to that shown in FIG. 11, and therefore, will not be described here.
FIG. 13 is an explanatory diagram showing the sequence of generating the logic function specifying data for the programmable emulator apparatus of FIG. 12. Likewise in the manufacturing apparatus of FIG. 11, the data processing device 52 is in charge of generation of the logic function specifying data.
Referring to FIG. 13, overall circuitry diagram data 61 are produced which define the whole configurable semiconductor integrated circuit device 1, and then stored on the magnetic disk 55 in an overall logic designing step 81.
Next, in a circuit dividing step 82, the overall circuitry diagram data 61 are divided in such a manner that the divided data can be each stored in each configurable semiconductor integrated circuit device 1. A plurality of divided circuitry diagram data 62 are outputted which correspond to the respective configurable semiconductor integrated circuit devices 1.
Following this, in an arranging and wiring step 83, each of the divided circuitry diagram data 62 are processed by an arranging and wiring treatment, thereby obtaining logic function specifying data 63 which correspond to the respective configurable semiconductor integrated circuit devices 1. The plurality of the logic function specifying data 63 are then temporarily stored on the magnetic disk 55. The arranging and wiring step 83 is performed in a similar manner to which the arranging and wiring step 12 shown in FIG. 10 is performed.
At last, after setting every one of the configurable semiconductor integrated circuit devices 1 into the logic function setting mode, the plurality of the logic function specifying data 63 stored on the magnetic disk 55 are each transferred to the memory elements 3 of the associated configurable semiconductor integrated circuit device 1 through the interface circuit 51, whereby desired logic functions are allotted to the respective configurable semiconductor integrated circuit devices 1.
The configurable semiconductor integrated circuit devices 1 are then set into the regular operation mode as the manufacturing apparatus of FIG. 11 is. Since the connector 7 is connected to the regular logic input/output terminals 6 of the configurable semiconductor integrated circuit devices 1, a signal available from an output terminal of the connector 7 represents aggregation of the logic functions of the configurable semiconductor integrated circuit devices 1. Hence, the signal obtainable from an output terminal of the connector 7 is equivalent to a signal which would be outputted from a large scale logic circuit having a large scale logic function.
Thus, a user can connect the connector 7 to predetermined parts of a target device 45 and regard an input/output signal of the connector 7 of the programmable emulator apparatus of FIG. 12 as an input/output signal of a large scale logic circuit which is under R&D process.
Therefore, by realizing equivalents for the logic functions of the wanted large scale logic circuit on the programmable emulator apparatus of FIG. 12 before actually developing the large scale logic circuit, the wanted logic functions can be evaluated concurrently with verification of the operations of the whole target device.
At the same time and separately from this, operations of the configurable semiconductor integrated circuit devices 1 for every predetermined time duration can be analyzed in detail by the logic signal analysis device 40. It is also possible to store the results of the analysis on the magnetic disk 55 under the control of the data processing device 52 and output the results of analysis on the display 53.
In general, "emulation" refers to manufacturing of a circuit which has the same logic function as that of a target semiconductor integrated circuit device but which is formed by different circuit parts and subsequent evaluation of both the logic function and overall operations of the target device under development, and these manufacturing and evaluation processes are executed before actual fabrication of the target device. A programmable emulator apparatus is capable of performing emulation of various large scale logic circuit only if the logic function specifying data for the configurable semiconductor integrated circuit devices 1 are changed.
Unlike a conventional programmable emulator apparatus in which a standard semiconductor device is assembled hardwired for each different target circuit to perform emulation, the programmable emulator apparatus of FIG. 12 realizes emulation only by changing the logic function specifying data. Hence, in the programmable emulator apparatus of FIG. 12, manual labor involved in emulation is largely reduced.
As heretofore described, fabrication of the conventional configurable semiconductor integrated circuit device requires to store the logic function specifying data in the memory elements of the configurable semiconductor integrated circuit device. For this reason, if a new logic function is to be set, the logic function specifying data 22 for realizing the desired new logic function must be generated by the data processing device 52.
The data processing device 52 is a device for unspecified use. Hence, the data processing device 52 sequentially performs various processings necessary to generate the logic function specifying data 22 on a software processing basis, and therefore, an extremely long time is demanded for development of the logic function specifying data 22. In the programmable emulator apparatus of FIG. 12 which is comprised of a plurality of the configurable semiconductor integrated circuit devices 1, in particular, the processing time increases in proportion to the number of the configurable semiconductor integrated circuit devices 1 employed therein.